1. Field of the Invention
The present invention relates to package substrates and fabrication methods thereof, and more particularly, to a package substrate having a semiconductor component embedded therein and a fabrication method thereof.
2. Description of Related Art
In addition to conventional wire bonding packages, the semiconductor industry developed, thanks to ever-evolving semiconductor packaging technology, various semiconductor device packages. For example, a package substrate embedded with and electrically integrated with a semiconductor chip having integrated circuits therein, as the latest mainstream, reduces the overall volume and thickness of a semiconductor device and enhances the electrical performance thereof.
Referring to FIGS. 1A through 1L, U.S. Pat. No. 6,586,276 discloses a conventional method for fabricating a package substrate having a semiconductor component embedded therein. Referring to FIG. 1A, the wafer 10 comprises a plurality of electrode pads 101. A passivation layer 11 is formed on the wafer 10 shown in FIG. 1B. The passivation layer 11 is provided with a plurality of first openings 110 therein so as to expose the electrode pads 101 therefrom as shown in FIG. 1C. Referring to FIG. 1D, the passivation layer 11 and the electrode pads 101 are covered with an adhesive layer 12. Referring to FIG. 1E, a protective layer 13 is formed on the surface of the adhesive layer 12. Referring to FIG. 1F, the wafer 10 is singularized into a plurality of semiconductor chips 10a. Referring to FIG. 1G, a substrate body 14 with an opening 140 is provided, and the semiconductor chip 10a is received in the opening 140 of the substrate body 14, and the gap between the opening 140 of the substrate body 14 and the semiconductor chip 10a is filled with a bonding material 15 such that the semiconductor chip 10a is fixed in position to the opening 140. Referring to FIG. 1H, a conductive layer 16 is formed on the protective layer 13 of the semiconductor chip 10a, bonding material 15 as well as the substrate body 14. A resist layer 17 is formed on the conductive layer 16 as shown in FIG. 1I. Next, a plurality of resist layer openings 170 corresponding in position to the electrode pads 101, respectively, are formed in the resist layer 17. Referring to FIG. 1J, expanded pads 18 are formed on the conductive layer 16 in the resist layer openings 170 by electroplating. Referring to FIG. 1K, the resist layer 17 and the conductive layer 16 covered therewith, the protective layer 13, and the adhesive layer 12 are removed to expose the expanded pads 18 and the passivation layer 11 therefrom, wherein the expanded pads 18 have a larger size than the electrode pads 101 to facilitate alignment of a wiring layer formed after lamination of a dielectric layer. Referring to FIG. 1L, a built-up structure 19 is further formed on the expanded pads 18, the passivation layer 11 and the substrate body 14; the built-up structure 19 comprising at least a dielectric layer 191, a wiring layer 192 stacked on the dielectric layer 191, and a plurality of conductive vias 193 formed in the dielectric layer 191 and electrically connected to the expanded pads 18. A plurality of electrical contact pads 194 are electrically connected to the wiring layer 192 and formed on the surface of the built-up structure 19. The built-up structure 19 is formed with an insulating protection layer 195 thereon. The insulating protection layer 195 is provided with a plurality of insulating protection layer openings 1950 for exposing the electrical contact pads 194 therefrom, respectively.
In the conventional method for fabricating a package substrate having a semiconductor component embedded therein described above, it is necessary to form the adhesive layer 12 on the passivation layer 11 and the electrode pads 101 in order to further form the protective layer 13 on the adhesive layer 12, singularizing the wafer 10 into a plurality of semiconductor chips 10a, fix the semiconductor chip 10a in position to the opening 140 of the substrate body 14 by a bonding material 15, form the expanded pads 18 on the adhesive layer 12 and the protective layer 13, and form the dielectric layer 191 of the built-up structure 19 on the semiconductor chip 10a with expanded pads 18, the bonding material 15, and the substrate body 14. That is, the semiconductor chip 10a is required to be secured in position to the opening 140 of the substrate body 14 by the bonding material 15 first, thereby increasing the complexity of manufacturing processes. What is more, the expanded pads 18 have to be formed on the electrode pads 101 of the semiconductor chip 10a so that the built-up structure 19 can be formed, and through the expanded pads 18, damage in the electrode pads 101 of the semiconductor chip 10a can be avoided while forming openings in the dielectric layer 191 of the built-up structure 19. As a result, the conventional fabrication method complicates manufacturing processes while forming expanded pads 18, and thus the manufacturing processes are neither time-efficient nor cost-efficient. In addition, the electrical connection structure including expanded pads 18 and the conductive vias 193 is very complicated.
Therefore, it is desired to provide a package substrate embedded with a semiconductor component and a fabrication method thereof to reduce the processing time and cost as well as to avoid the structural complexity.